1. Field of the Invention
The present invention relates to a circuit topography which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature (300° C. to 500° C. and higher) silicon carbide (SiC) device production.
2. Description of the Related Art
There are current reasons for placing intelligent processing near or within sources of high temperature on the order of, for example, 300° C. and higher. Electronic components for use in these temperatures are typically made of silicon carbide (SiC), which can operate in temperatures as high as 600° C. However, processing, either in an analog domain or a digital domain, requires components whose parameters are closely matched, and as a consequence, often exist on the same die, as in integrated circuits. Current processing needs exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits.
It is currently possible to produce a single component to small number of components of (negatively doped) N channel Junction Field Effect Transistors (JFETs) and epitaxial resistors on a single substrate. In order to produce these components, the quest was to find a way to synthesize usable logic blocks from these devices, knowing that parameters such as gate to source turn off voltage and drain saturation current, may vary from part to part by multiples of five to ten.
These parameter distribution issues precluded conventional direct coupled and buffered direct coupled FET logic techniques which depend upon precise manipulation and matching of transistor channel widths. Other logic techniques required mixes of complementary P (positively doped) and N (negatively doped) channel devices or mixes of depletion and enhancement mode devices. These other technologies typically worked at temperatures no greater than 125° C., for silicon, with various other technologies operational from 225° C. up to 400° C. As stated earlier, SiC can operate in temperatures up to 600° C.
The lack of precise device to device control over device parameters in discrete SiC JFET production and the lack of complementary devices created the need to use resistors as loads and as level shifters. Thus, in the current state of the art, one would normally use current sources, push pull stages or dropping diodes available using lower temperature technologies to configure logic gates.
If one creates a method to produce these logic functions of inversion, combination and latching, one would bring basic intelligent capability to devices operating in harsh thermal environments. For example, one could create a SiC pressure sensor in a jet engine with a frequency output which could have its output sent through a binary polynomial generator created out of SiC flip-flops and exclusive OR gates. If the output frequency of the sensor is logically ANDed with the output of the generator, a unique envelope would be associated with that sensor and when detected by a radio receiver, the signal could be demodulated in a correlation space and differentiated from all the other sensors using different polynomials. A further example would be a surface rover on Venus which uses a simple digital state machine for decision making and control, allowing it to exhibit useful behaviors.